function result = file_write(file_name)
%   pc_bee4_ddr3_rw -- Download and upload data between PC and BEE4
%   using pc_bee4_ddr3_rw.mdl
%
%   This function demonstrates how to upload data to the
%   on-FPGA Block RAM, store data to DDR3 memory, transfer data back to
%   another on-FPGA Block RAM, and download from the on-FPGA Block RAM.
%
%   Example using the function is:
%     abc = 1:1024*1024/4;
%     close all;
%     fid = fopen('file.dat','wb');
%     fwrite(fid,abc,'uint32');
%     close all;
%     result = pc_bee4_ddr3_rw('192.168.0.100', 'A','file.dat',0);
%
%   The arguments to the function are the address/hostname of the BEE4
%   system, ID of the FPGA running the FMC101 reference design, file name
%   to be upload to FPGA and data length, respectively.
%   Valid FPGA IDs are 'A', 'B', 'C', or 'D'.
%   length of the data is represented by KBytes. eg. 1 means upload
%   1KBytes. 0 means upload the whole file.
%   Please note that there may not be any serial port terminals open on
%   the BEE4 system, or else the underlying hardware operations will fail.

switch nargin
    case 1
        if ~ischar(file_name),error('file name must be a string'); end
    otherwise
        error('Wrong number of input arguments');
end

fid = fopen(file_name,'wb');
if fid == -1
    error('Output File can not be opened for write');
end

%% main write process
%% write data

data_length = 32;
value = 32
i = value;
j = data_length;
result = data_length * value;
while j ~= 0
    while i ~=0
    % write to file
    fwrite(fid,i,'uint8');
    i = i - 1;
    end
    i = value;
    j = j - 1;
end
fprintf('write file done !\n');
fclose all;

end

